1. Field of the Invention
This invention relates to the field of integrated circuit manufacturing. More particularly, the present invention describes a method for using manufacturing defect data in order to increase the throughput of integrated circuit manufacturing equipment.
2. Background
Improvements in integrated circuit technology have resulted in the gradual increase in the overall size of individual wafers and the dramatic decrease in the die area required to perform a given function. Thus, greater numbers of more complex circuits are now present on each wafer. For example, the number of bits stored in a leading edge Dynamic Random Access Memory (DRAM) has increased about a thousand times over the past fifteen years.
Due to the high cost of the manufacturing equipment and other equipment used to produce an integrated circuit, it is desirable to maximize the throughput of the manufacturing process so as to amortize the cost of the equipment over the highest number of wafers possible in a given amount of time.
When manufacturing electronic circuits on silicon wafers, it is common to perform all processing, inspection, and test operations on each die within each wafer so that each die is manufactured as nearly identically as possible. As integrated circuit technology has evolved, manufacturing and inspection techniques have been developed for improving the yield of good dice and for identifying the physical origins of failures. For example, inspection stations utilizing automated optical inspection techniques allow inspection of large areas of the wafer simultaneously in order to provide high throughputs which decreases the cost of inspection per layer per wafer.
Typical optical inspection stations are computer controlled and are capable of generating reports on defect density by defect size by process layer inspected for each wafer inspected. This information, together with the location of the defects, is either stored locally at each inspection station, or stored in a large data base. This data is often used with statistical techniques in a statistical process control (SPC) system to provide feedback to manufacturing personnel which might indicate when to perform maintenance operations or when a manufacturing tool is out of statistical control and consequently in need of intervention by a technician.
Not all defects caused during the manufacturing process will cause electrical malfunctions. Whether a particular defect causes a fault depends upon where the defect lies, its size, and whether it is comprised of conducting or non-conducting material.
FIG. 1 is a layout diagram of typical defects which will not result in an electrical failure.
Referring to FIG. 1, conductive paths 10 and 12 represent conducting metal layers that are not designed to be connected together. Regions 14 and 16 represent areas of unintended metal remaining on the wafer after a metal etch processing step. Neither of these regions 14 or 16 cause an unintended connection between paths 10 and 12, and thus are termed "non-fatal" defects. If either of these defects was large enough that paths 10 and 12 were caused to be connected, the region 14 or 16 which connected them would be designated a fatal defect.
The analysis to determine whether defects are fatal can be performed without electrical testing using only geometrical information. However, this will often lead to a false positive identification of fatal defects.
FIG. 2 is a layout diagram depicting defects which cause bridging between traces.
Referring to FIG. 2, conductive paths 20 and 22 represent portions of a metal layer such as the metal-1 or metal-2 layers known to those of ordinary skill in the art. Defects 24 and 26, if comprised of conducting material, have the potential of electrically connecting the two neighboring traces, thus causing one or more "bridging" faults. The determining factor of whether a bridging fault would occur is whether those neighboring traces are designed to be connected at some other location on the die. If the traces are not designed to be connected at any location, a bridging fault exists.
For example, because the two portions 28 and 30 of path 20 are designed to be connected together near the reference designation 20, defect 24 causes a non-fatal defect bridge between portions 28 and 30 of path 20. Because the bridge does not connect two traces that otherwise would not be connected, there is no bridging fault.
A second example involves portion 30 of path 20, and portion 32 of path 22. Here, if region 34 is a trace on an upper layer (isolated from the lower layer by a dielectric) which connects path 20 and 22 at contact points 36 and 38 respectively, defect 26 will be a nonfatal defect. However, if region 34 was not there, defect 26 would, in this second example, be fatal. This is because path 20 and 22 are not designed to be connected, but the unintentional conductive defect 26 has connected them. Thus, whether a defect causes a fault depends not only on the size and location of the defect, but also on its conductivity and upon the connectivity of the traces that are potentially affected.
Integrated circuits (IC's) are comprised of multiple layers of different materials, with each layer interacting with other layers in various ways depending on the materials involved. Typically, an IC that results from a manufacturing and packaging process began as a blank silicon wafer regions of which have been suitably doped and, upon which layers of metal, dielectric, and perhaps other materials have been formed. Patterns on a wafer are typically formed by applying a layer of a desired material, upon which a photosensitive material (photoresist) is applied. The photosensitive material on the wafer is then selectively exposed to a high intensity ultraviolet (UV) light from a mercury arc lamp, a laser, or other similar source through a mask, and then developed in a chemical to remove the photosensitive material from areas on the wafer which were not exposed to the UV light. Chemicals in a liquid solution or gaseous plasma are then employed to selectively remove material from regions not covered by photoresist, while regions covered by photoresist are protected and thus remain intact. Finally, the photoresist is removed. This process is carried out repeatedly to build up the electronic circuits on the wafer. A single wafer comprises many dice, and each functional die eventually is cut from the wafer and packaged for use as an IC in an electronic device.
The photosensitive material used in the lithography process is an organic polymer that is referred to as photoresist. In order to form very small features in the photoresist having close registration with features that have been formed in previous operations, it is common practice to expose only a small portion or "field" of the photoresist-covered wafer through a mask or stencil, expose a second field offset from the first, repeating the exposing process for all fields on the wafer. This process is referred to as "stepping" the mask image across the wafer. One field may contain several die.
Prior art wafer manufacturing operations are typically performed on each die section of each wafer, proceeding until each die on a given wafer has received identical or nearly identical processing treatment. Although suitable for its intended purpose, the prior art fails to maximize throughput of manufacturing equipment in cases where further processing on a die containing fatal defects would be useless. It would therefore be beneficial to provide a method for intelligently using defect data in the manufacturing process to eliminate from further processing those die location which contain defects which are determined to be fatal.